1.1. Field of the Invention
The present invention relates to the field of hardware settings in multiprocessor systems or in multiprocessor core systems. In particular, it relates to a method and respective system for updating scan chain settings of selected processors comprised of a multiprocessor system in cooperation with a support hardware or a service interface for said system, preferably comprising one or more support processors, which allow to insert new defect-free scan chain data to one or more processors, or processor cores, respectively.
1.2. Description of Related Art
In the context of this application the term “processor” is an abstraction that was first implemented as multiple chips, later-on as single chips, nowadays often as multiple cores on a single chip. Thus, for the sake of clearness, the term comprises all of said different meanings.
Prior art is described in the published US patent application US 2008/0028266 A1, and in U.S. Pat. No. 7,568,138 B2, which are incorporated by reference.
FIG. 1 illustrates the most basic structural components of a prior art hardware environment used for a prior art method.
FIG. 1 shows an exemplary prior art configuration of a symmetric multiprocessor consisting of one or multiple processor nodes 401. Each processor node holds one of more processor chips and each processor chip has one or more processor cores. Also located on each processor chip are components such as Cache, fabric bus, memory controller, etc., as described in more detail in U.S. Pat. No. 7,568,138 B2. In this document these components are referred to as the chip nest 405. Each processor core is connected to the chip nest via a set of interfaces that can be fenced; e.g., in the case that a processor core is stopped due to a hardware defect. This means that all outgoing lines are set to inactive.
Also located on each processor chip are the pervasive controls 406 which provide a scan access from the Support Processor 407 to all processor cores as well as to each chip nest. It also establishes a communication path between firmware running on the support processor and firmware running on the processor cores. One appointed processor core 409 is the communication (e.g., along communication line 410) counterpart for the Support Processor 407.
In order to update scan chain settings as mentioned before in above systems according to prior art, mechanisms are used in which a hardware reset sets the multiple chips into a functional state that allows for further initialization by a service processor. Without this initialization step a processor is not capable to run. The service processor sets up so-called “scan only” latches and starts the processor clock. As of today, new settings or modified settings of these initial values are exclusively done during the power-on-reset phase, which is disadvantageously disruptive for customer operations.
Further, in prior art, processors of the x86 processor architecture family may perform updates of the settings only in-band after the processor clocks have been started. This, however, requires a lot of dedicated hardware efforts and limits the scope of changes that can be applied.